Field of the Invention
The present invention relates to a semiconductor device and a method for producing a semiconductor device.
Description of the Related Art
In recent years, magnetoresistive random access memories have been developed (refer to, for example, Japanese Unexamined Patent Application Publication No. 2013-93592).
In the typical structure of a spin-transfer torque magnetoresistive random access memory (STT-MRAM) array illustrated in FIG. 6B of Japanese Unexamined Patent Application Publication No. 2013-93592, a source line (SL) is parallel to word lines (WL) and is perpendicular to bit lines (BL). In the case where this structure is formed using planar transistors, as illustrated in FIG. 6B of the publication, one source line is necessary for two memory cells, and one source line is arranged between word lines. This layout increases the area used for a bit-cell array and has large bit-cell dimensions.
A surrounding gate transistor (hereinafter referred to as “SGT”) having a structure in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and a gate electrode surrounds a pillar-shaped semiconductor layer has been proposed (refer to, for example, Japanese Unexamined Patent Application Publication No. 2004-356314).
With a decrease in the width of a silicon pillar, it becomes more difficult to allow an impurity to be present in the silicon pillar because the density of silicon is 5×1022 atoms/cm3.
In a typical SGT, it has been proposed that an impurity concentration of a channel is set to be a low concentration of 1017 cm−3 or less, and the threshold voltage is determined by changing the work function of a gate material (refer to, for example, Japanese Unexamined Patent Application Publication No. 2004-356314).
It has been disclosed that, in a planar MOS transistor, the sidewall of a lightly doped drain (LDD) region is formed of a polycrystalline silicon having the same conductivity type as a low-concentration layer, surface carriers of the LDD region are induced by the difference in work function, and the impedance of the LDD region can be reduced compared with oxide film sidewall LDD-type MOS transistors (refer to, for example, Japanese Unexamined Patent Application Publication No. 11-297984). It has also been disclosed that the polycrystalline silicon sidewall is electrically insulated from a gate electrode. The drawings of the publication illustrate that the polycrystalline silicon sidewall is insulated from a source and a drain by an interlayer insulating film.